To MIPS or Not to MIPS, That is the CP Question!

Processors used to be simple: they ran at a fixed instruction rate, and capacity planning was based on MIPS (Millions of Instructions Per Second). In addition to being immensely larger, today's System z processors are much more complex and sophisticated. Features such as PR/SM, the number of CPs, workload mixes, millicode, specialty engines, and cache structures all affect processor performance and capacity. During this presentation the speaker will discuss these issues and offer some suggestions on when to use MIPS for capacity planning, and when MIPS is merely a Misleading Indicator of Processor Speed.

This session was presented previously, but it has been updated with zEnterprise zEC12 experience